We consider the design of an efficient FSE/DFE-based HDSL equalizer. For this, various variants of the conventional LMS algorithm and their delayed versions are investigated. In addition, two new adaptive algorithms are also studied which yield lower computational complexity but similar performance when compared to conventional algorithms. We also propose a way to initialize the DFE coefficients for fast convergence. Extensive simulation is conducted to evaluate various algorithms' performance and to facilitate hardware design. Due to time constraint, the present design employs a conventional algorithm. It is verified with the Verilog and Opus VLSI CAD tools. Layout design of the equalizer chip has been taped out for foundry fabrication.