An efficient design for one-dimensional discrete hartley transform using parallel additions

Jiun-In Guo*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

17 Scopus citations

Abstract

This paper presents a new efficient design for the onedimensional (1-D) any-length discrete Hartley transform (DHT). Using the similar idea to the Chirp-Z transform, an algorithm that can formulate the 1-D any-length DHT as cyclic convolutions is developed. This algorithm owns higher flexibility in the transform length as compared with the existing approaches for prime length DHT or power-of-two DHT designs. Moreover, the proposed design exploits the good feature of cyclic convolution and uses parallel adders instead of multipliers in the hardware realization. The presented design not only possesses low hardware cost but also owns low input/output (I/O) cost, high computing speeds, and flexibility in transform length.

Original languageEnglish
Pages (from-to)2806-2813
Number of pages8
JournalIEEE Transactions on Signal Processing
Volume48
Issue number10
DOIs
StatePublished - 1 Oct 2000

Keywords

  • Convolution
  • Discrete hartley transforms
  • Parallel architectures

Fingerprint Dive into the research topics of 'An efficient design for one-dimensional discrete hartley transform using parallel additions'. Together they form a unique fingerprint.

Cite this