An Efficient Decoder Architecture for Nonbinary LDPC Codes with Extended Min-Sum Algorithm

Chia Lung Lin*, Shu Wen Tu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

Nonbinary low-density-parity-check (NB-LDPC) codes, an extension of binary LDPC codes, provide stronger error-correcting capability than binary LDPC codes. However, the performance gain comes together with extraordinary increase on decoding complexity and memory requirement. Many simplification algorithms have been proposed in the literature, and the extended min-sum (EMS) algorithm is the one with minimal performance loss. In this brief, we present an efficient decoder architecture for quasi-cyclic NB-LDPC codes with the EMS algorithm. The throughput is improved by not only the double-throughput elementary check node unit but also overlapped processing for both check node and variable node units (VNUs). To reduce memory usage and computing complexity, edge-message hiding and simplified VNU are proposed as well. With these schemes, the postlayout results of a decoder for a (112, 56) NB-LDPC over GF(64) are presented. The core area occupies 2.24 mm2 and consumes 274 mW with a throughput of 124.6 Mb/s. Compared to prior NB-LDPC decoders with a similar code rate, the proposed decoder achieves better hardware efficiency and energy efficiency.

Original languageEnglish
Article number7419880
Pages (from-to)863-867
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume63
Issue number9
DOIs
StatePublished - 1 Sep 2016

Keywords

  • Decoding scheduling
  • extended min-sum (EMS) algorithm
  • nonbinary low-density-parity-check (NB-LDPC) codes
  • Very large scale integration (VLSI)

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