An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs

Chin Cheng Kuo*, Yu Chien Wang, Chien-Nan Liu

*Corresponding author for this work

Research output: Contribution to conferencePaper

5 Scopus citations

Abstract

In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL circuits more quickly by using Verilog-AMS language. Not only top-down applications but also bottom-up applications can be supported by using our PLL models. The main idea is to use a special "characterization mode" to get critical circuit parameters. In the characterization mode, only two input patterns are enough to get circuit properties with parasitic effects. In the experimental results, we will build an accurate PLL behavioral models for demonstration compared to the HSPICE results and typical behavioral models.

Original languageEnglish
Pages286-290
Number of pages5
DOIs
StatePublished - 29 Dec 2005
Event2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States
Duration: 17 Apr 200519 Apr 2005

Conference

Conference2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
CountryUnited States
CityChicago, IL
Period17/04/0519/04/05

Fingerprint Dive into the research topics of 'An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs'. Together they form a unique fingerprint.

  • Cite this

    Kuo, C. C., Wang, Y. C., & Liu, C-N. (2005). An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. 286-290. Paper presented at 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05, Chicago, IL, United States. https://doi.org/10.1145/1057661.1057730