An efficient binary motion estimation algorithm and its architecture for MPEG-4 shape encoding

Esam A. Al-Qaralleh; Tian-Sheuan Chang; Kun Bin Lee

doi:10.1109/TCSVT.2006.878148

An efficient binary motion estimation algorithm and its architecture for MPEG-4 shape encoding

Esam A. Al-Qaralleh^*, Tian-Sheuan Chang, Kun Bin Lee

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

This paper presents a fast binary motion estimation (BME) algorithm and its architecture for MPEG-4 shape encoding. The proposed algorithm explores the property of the binary-value in BME to quickly skip the unnecessary sum of absolute differences (SAD) computation. When comparing with the full search algorithm, simulation results show that it can efficiently save in the search positions to an average -99.58% of that in the full search algorithm with the same PSNR quality. Due to the algorithm's simplicity and regularity, the resulting hardware implementation also exhibits simple and regular control and data flow. It can achieve real-time encoding with only 11582 gate count.

Original language	English
Article number	1661661
Pages (from-to)	859-868
Number of pages	10
Journal	IEEE Transactions on Circuits and Systems for Video Technology
Volume	16
Issue number	7
DOIs	https://doi.org/10.1109/TCSVT.2006.878148
State	Published - 1 Jul 2006

Keywords

Binary motion estimation(BME)
MPEG-4
Shape coding
Video object plane (VOP)

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AB - This paper presents a fast binary motion estimation (BME) algorithm and its architecture for MPEG-4 shape encoding. The proposed algorithm explores the property of the binary-value in BME to quickly skip the unnecessary sum of absolute differences (SAD) computation. When comparing with the full search algorithm, simulation results show that it can efficiently save in the search positions to an average -99.58% of that in the full search algorithm with the same PSNR quality. Due to the algorithm's simplicity and regularity, the resulting hardware implementation also exhibits simple and regular control and data flow. It can achieve real-time encoding with only 11582 gate count.

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