This paper presents a low latency and area-efficient architecture for key equation solver (KES) in decoding BCH codes. We modify simplified inversionless Berlekamp-Massey (SiBM) algorithm by rescheduling initial value and removing the idle part during computation. Compared with the original SiBM algorithm, our new architecture implemented in BCH (18244, 16384; 124) code can save 42% gate-count within t cycles. Moreover, the proposed KES can simultaneously support 8-channel syndrome generators and Chien search logics to achieve 12.6Gb/s throughput under 198MHz operation frequency.
|Number of pages||4|
|State||Published - 1 Dec 2012|
|Event||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan|
Duration: 12 Nov 2012 → 14 Nov 2012
|Conference||2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012|
|Period||12/11/12 → 14/11/12|