An efficient BCH decoder with 124-bit correctability for multi-channel SSD applications

Hung Yuan Tsai, Chi Heng Yang, Hsie-Chia Chang

Research output: Contribution to conferencePaperpeer-review

4 Scopus citations

Abstract

This paper presents a low latency and area-efficient architecture for key equation solver (KES) in decoding BCH codes. We modify simplified inversionless Berlekamp-Massey (SiBM) algorithm by rescheduling initial value and removing the idle part during computation. Compared with the original SiBM algorithm, our new architecture implemented in BCH (18244, 16384; 124) code can save 42% gate-count within t cycles. Moreover, the proposed KES can simultaneously support 8-channel syndrome generators and Chien search logics to achieve 12.6Gb/s throughput under 198MHz operation frequency.

Original languageEnglish
Pages61-64
Number of pages4
DOIs
StatePublished - 1 Dec 2012
Event2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan
Duration: 12 Nov 201214 Nov 2012

Conference

Conference2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
CountryJapan
CityKobe
Period12/11/1214/11/12

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