An efficient approach to build accurate behavioral models of PLL designs

Chin Cheng Kuo*, Yu Chien Wang, Chien-Nan Liu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


In this paper, an efficient bottom-up extraction approach is presented to generate accurate behavioral models of PLL designs more quickly by using Verilog-AMS language. The main idea is to use a special "characterization mode" such that we can use only one input pattern to get all required circuit parameters with parasitic effects. After carefully adjustment, all parameters in our behavioral models can be measured at the outputs of the PLL system without simulating each block separately. Therefore, this approach is more suitable to accurately model protected IPs or flattened post-layout netlists. In the experimental results, we will build an accurate PLL behavioral model for demonstration and compare the results with HSPICE simulation and traditional behavioral models.

Original languageEnglish
Pages (from-to)391-398
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number2
StatePublished - 1 Jan 2006


  • Analog behavioral model
  • Bottom-up extraction
  • IP
  • PLL

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