An Efficient 2-D DCT/IDCT Core Design Using Cyclic Convolution and Adder-Based Realization

Jiun-In  Guo*, Rei Chin Ju, Jia Wei Chen

*Corresponding author for this work

Research output: Contribution to journalArticle

30 Scopus citations

Abstract

This paper proposes an efficient two-dimensional (2-D) discrete cosine and inverse discrete cosine transform (DCT/IDCT) core design. Adopting the row-column decomposition technique for computing 2-D DCT/IDCT, we formulate the one-dimensional (1-D) DCT/IDCT into cyclic convolution by properly arranging the input sequence, optimize the multiplications based on the concept of common subexpression sharing, and carry out the multiplications through carry-save adders (CSAs). Using cyclic convolution is helpful in exploiting the word-level data sharing in computing different DCT/IDCT outputs. Adopting the common subexpression sharing is beneficial to the bit-level data sharing in computing the outputs. As compared with some existing approaches of realizing DCT/IDCT, the proposed approach can save on average 20%-33% in the delay-area product (gate-count * time-unit) based on a 0.35-μm CMOS technology under the data word-lengths ranging from 16-24 b. Besides, we have also proposed an IP generator for designing the 2-D DCT/IDCT based on the proposed approach. It provides a design-automation environment with parameter configurations in designing a 2-D DCT/IDCT core that is suitable for most image and video compression applications.

Original languageEnglish
Pages (from-to)416-428
Number of pages13
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume14
Issue number4
DOIs
StatePublished - 1 Apr 2004

Keywords

  • Binary signed digit representation
  • Common subexpression sharing
  • Cyclic convolution
  • Digital IP design
  • Discrete cosine transform (DCT)
  • Image compression
  • Inverse discrete cosine transform (IDCT)
  • SOC design
  • Video compression

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