An automated IP synthesizer for limited-resource DWT processor

Ting Hsun Wei, Shiuh Rong Huang, Lan-Rong Dung

Research output: Contribution to journalArticlepeer-review


This paper presents a systematic design methodology for 1-D/2-D DWT processor based on a novel limited-resource scheduling algorithm. Given a set of architecture constraints and DWT parameters, the scheduling algorithm can generate four scheduling matrices that drive the data path to perform the DWT computation. Based on the limited-resource scheduling algorithm an automated DWT processor synthesizer has been developed and generates constrained DWT processors in the form of silicon intelligent property (SIP). The DWT SIP can be embedded into a SOC or mapped to program codes for commercial off-the-shelf (COTS) DSP processors with programmable devices. As a result, it has been successfully proven that a variety of DWT SIPs can be efficiently realized by tuning the parameters and applied for signal processing applications.

Original languageEnglish
Article number5745323
Pages (from-to)3172-3175
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
StatePublished - 13 May 2002

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