An area-efficient median filtering IC for image/video applications

Po Wen Hsieh, Jer Min Tsai, Chen-Yi Lee

Research output: Contribution to journalArticlepeer-review


An area-efficient IC for high-throughput median filtering applications is presented in this paper. This IC implements a modified delete-and-insert sorting algorithm which is very efficient for running order statistics applications. In hardware design, we first map the algorithm onto a regular PE structure, where each PE consistis of shift register, comparator, and some control gates. Then we conduct full-custom circuit/layout design of the PE to meet performance requirement. A proto-type chip for 64 input samples is implemented and tested. Results show that clock rate up to 50 MHz can be achieved using a 1.2 µm CMOS double metal technology. Two outstanding features of this IC are: (1) any specified order of input patterns can be produced within one clock cycle; (2) each chip can handle at most 64 data and can be cascaded as the number of sorted data is over 64. Thus this IC releases the bottle-neck of median search in hardware realization for many system designs, making real-time performace achievable.

Original languageEnglish
Pages (from-to)504-509
Number of pages6
JournalIEEE Transactions on Consumer Electronics
Issue number3
StatePublished - 1 Jan 1993

Fingerprint Dive into the research topics of 'An area-efficient median filtering IC for image/video applications'. Together they form a unique fingerprint.

Cite this