An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving

Ramy Yousry; Ming Shuan Chen; Mau-Chung Chang; Chih Kong Ken Yang

doi:10.1109/ASSCC.2013.6691038

An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving

Ramy Yousry, Ming Shuan Chen, Mau-Chung Chang, Chih Kong Ken Yang

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

This paper introduces the design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS. Accuracy requirements are met without compromising performance by means of digital calibration and smart architecture selection. Partial interleaving architecture and the introduction of a current-steering DAC and an open-loop residue amplifier are proposed to relax the MDAC settling at minimal overhead. Dynamic thresholds adjustment for the sub-ADCs is employed both to calibrate the ADC offset mismatches and to correct for the residue amplifier nonidealities. The ADC covers a resolution range from 3-b to 7-b at sampling rates from 4GS/s to 1.5GS/s. The worst case DNL and INL are ±0.45LSB and ±0.66LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv at 7-b and occupies an active area of 0.15mm ².

Original language	English
Title of host publication	Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Pages	285-288
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2013.6691038
State	Published - 1 Dec 2013
Event	2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore, Singapore Duration: 11 Nov 2013 → 13 Nov 2013

Publication series

Name	Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Conference

Conference	2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013
Country	Singapore
City	Singapore
Period	11/11/13 → 13/11/13

Access to Document

10.1109/ASSCC.2013.6691038

Link to publication in Scopus

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Yousry, R., Chen, M. S., Chang, M-C., & Yang, C. K. K. (2013). An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving. In Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 (pp. 285-288). [6691038] (Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013). https://doi.org/10.1109/ASSCC.2013.6691038

@inproceedings{7290a82dff0044e0a2f61a2bde3400a7,

title = "An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving",

abstract = "This paper introduces the design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS. Accuracy requirements are met without compromising performance by means of digital calibration and smart architecture selection. Partial interleaving architecture and the introduction of a current-steering DAC and an open-loop residue amplifier are proposed to relax the MDAC settling at minimal overhead. Dynamic thresholds adjustment for the sub-ADCs is employed both to calibrate the ADC offset mismatches and to correct for the residue amplifier nonidealities. The ADC covers a resolution range from 3-b to 7-b at sampling rates from 4GS/s to 1.5GS/s. The worst case DNL and INL are ±0.45LSB and ±0.66LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv at 7-b and occupies an active area of 0.15mm 2.",

author = "Ramy Yousry and Chen, {Ming Shuan} and Mau-Chung Chang and Yang, {Chih Kong Ken}",

year = "2013",

month = dec,

day = "1",

doi = "10.1109/ASSCC.2013.6691038",

language = "English",

isbn = "9781479902781",

series = "Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013",

pages = "285--288",

booktitle = "Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013",

note = "null ; Conference date: 11-11-2013 Through 13-11-2013",

}

Yousry, R, Chen, MS, Chang, M-C & Yang, CKK 2013, An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving. in Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013., 6691038, Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, pp. 285-288, 2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, Singapore, Singapore, 11/11/13. https://doi.org/10.1109/ASSCC.2013.6691038

An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving. / Yousry, Ramy; Chen, Ming Shuan; Chang, Mau-Chung; Yang, Chih Kong Ken.

Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013. 2013. p. 285-288 6691038 (Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving

AU - Yousry, Ramy

AU - Chen, Ming Shuan

AU - Chang, Mau-Chung

AU - Yang, Chih Kong Ken

PY - 2013/12/1

Y1 - 2013/12/1

N2 - This paper introduces the design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS. Accuracy requirements are met without compromising performance by means of digital calibration and smart architecture selection. Partial interleaving architecture and the introduction of a current-steering DAC and an open-loop residue amplifier are proposed to relax the MDAC settling at minimal overhead. Dynamic thresholds adjustment for the sub-ADCs is employed both to calibrate the ADC offset mismatches and to correct for the residue amplifier nonidealities. The ADC covers a resolution range from 3-b to 7-b at sampling rates from 4GS/s to 1.5GS/s. The worst case DNL and INL are ±0.45LSB and ±0.66LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv at 7-b and occupies an active area of 0.15mm 2.

AB - This paper introduces the design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS. Accuracy requirements are met without compromising performance by means of digital calibration and smart architecture selection. Partial interleaving architecture and the introduction of a current-steering DAC and an open-loop residue amplifier are proposed to relax the MDAC settling at minimal overhead. Dynamic thresholds adjustment for the sub-ADCs is employed both to calibrate the ADC offset mismatches and to correct for the residue amplifier nonidealities. The ADC covers a resolution range from 3-b to 7-b at sampling rates from 4GS/s to 1.5GS/s. The worst case DNL and INL are ±0.45LSB and ±0.66LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv at 7-b and occupies an active area of 0.15mm 2.

UR - http://www.scopus.com/inward/record.url?scp=84893583279&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2013.6691038

DO - 10.1109/ASSCC.2013.6691038

M3 - Conference contribution

AN - SCOPUS:84893583279

SN - 9781479902781

T3 - Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

SP - 285

EP - 288

BT - Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Y2 - 11 November 2013 through 13 November 2013

ER -