@inproceedings{7290a82dff0044e0a2f61a2bde3400a7,
title = "An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving",
abstract = "This paper introduces the design of a high-speed reconfigurable analog-to-digital converter in 65-nm CMOS. Accuracy requirements are met without compromising performance by means of digital calibration and smart architecture selection. Partial interleaving architecture and the introduction of a current-steering DAC and an open-loop residue amplifier are proposed to relax the MDAC settling at minimal overhead. Dynamic thresholds adjustment for the sub-ADCs is employed both to calibrate the ADC offset mismatches and to correct for the residue amplifier nonidealities. The ADC covers a resolution range from 3-b to 7-b at sampling rates from 4GS/s to 1.5GS/s. The worst case DNL and INL are ±0.45LSB and ±0.66LSB respectively. The ADC achieves a figure-of-merit of 0.46pJ/conv at 7-b and occupies an active area of 0.15mm 2.",
author = "Ramy Yousry and Chen, {Ming Shuan} and Mau-Chung Chang and Yang, {Chih Kong Ken}",
year = "2013",
month = dec,
day = "1",
doi = "10.1109/ASSCC.2013.6691038",
language = "English",
isbn = "9781479902781",
series = "Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013",
pages = "285--288",
booktitle = "Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013",
note = "null ; Conference date: 11-11-2013 Through 13-11-2013",
}