An analytical placer for heterogeneous FPGAs via rough-placed packing

Wan Ning Wu, Chen Chen, Ching Yu Chin, Chun Kai Wang, Hung-Ming Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Packing and placement are two crucial stages for FPGA realization. In the design flow, the basic logic units, such as look-up-tables (LUTs) and flip-flops (FFs), have to be merged into configurable logic blocks (CLBs) before placement. How the basic logic blocks are clustered in the packing stage has a great impact on the placement quality. This work presents an analytical placement framework for heterogeneous FPGAs through a rough-placed packing algorithm. In the packing stage, we first perform a fast wirelength-driven placement for the basic logic units. With the physical information from the initial placement, we implement an affinity-based clustering algorithm while taking the control signal constraints into consideration. In the placement stage, a quadratic global placer is implemented with the techniques of handling the heterogeneity, routing congestion estimation and cell inflation. An incremental placer is performed after the global placement for closing the gap between the global placement and legalization, and a detailed placer is adopted to legalize the blocks and reduce the wirelength. Experimental results show that the proposed methodologies can effectively improve the placement solutions.

Original languageEnglish
Title of host publication2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509039692
DOIs
StatePublished - 5 Jun 2017
Event2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan
Duration: 24 Apr 201727 Apr 2017

Publication series

Name2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

Conference

Conference2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
CountryTaiwan
CityHsinchu
Period24/04/1727/04/17

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