An analytical placer for heterogeneous FPGAs via rough-placed packing

Packing and placement are two crucial stages for FPGA realization. In the design flow, the basic logic units, such as look-up-tables (LUTs) and flip-flops (FFs), have to be merged into configurable logic blocks (CLBs) before placement. How the basic logic blocks are clustered in the packing stage has a great impact on the placement quality. This work presents an analytical placement framework for heterogeneous FPGAs through a rough-placed packing algorithm. In the packing stage, we first perform a fast wirelength-driven placement for the basic logic units. With the physical information from the initial placement, we implement an affinity-based clustering algorithm while taking the control signal constraints into consideration. In the placement stage, a quadratic global placer is implemented with the techniques of handling the heterogeneity, routing congestion estimation and cell inflation. An incremental placer is performed after the global placement for closing the gap between the global placement and legalization, and a detailed placer is adopted to legalize the blocks and reduce the wirelength. Experimental results show that the proposed methodologies can effectively improve the placement solutions.