An Analog Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT)

Yuan Du, Li Du, Xuefeng Gu, Jieqiong Du, X. Shawn Wang, Boyu Hu, Mingzhe Jiang, Xiaoliang Chen, Subramanian S. Iyer, Mau-Chung Chang

Research output: Contribution to journalArticlepeer-review

11 Scopus citations

Abstract

An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog-digital interfaces. By implementing the sequential analog fabric (SAF), the engine’s mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28nm CMOS technology and occupies 0.68mm². The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem – classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.

Original languageEnglish
Pages (from-to)1811-1819
Number of pages9
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume38
Issue number10
DOIs
StatePublished - 24 Jul 2018

Keywords

  • Analog computing engine.
  • Arrays
  • Artificial neural networks
  • Charge-trap transistors
  • Energy efficiency
  • Engines
  • Fully-connected neural networks
  • Logic gates
  • Neural networks
  • Transistors

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