An ALU cluster intellectual property for magnetic RAM media applications platform

Chia Yi Liou*, Her-Ming Chiueh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The next generation memory, Magnetic Random Access Memory (MRAM), is a high-profile choice of embedded memory in modern applications. Features of the novel memory make it suitable for universal memory applications. Besides, as the evolution of information technology, embedded systems with media applications for portable devices are more important in modern life. In both of the perspectives mentioned above, a processing element called Arithmetic Logic Unit (ALU) cluster Intellectual Property (IP) is designed and implemented to be integrated with MRAM and the platform baseboard in this work. To stack these components such as an ALU cluster, MRAM and versatile baseboard provides a development, verification and demonstration platform for the highly-expected MRAM. The proposed ALU cluster IP with Advanced Microcontroller Bus Architecture (AMBA) interface is taped out using TSMC 0.15um technology and operates at 100MHz. The chip area is 3.9*3.9 mm2 and gate count is 0.2 million. A 4-layer FRP printed circuit board (PCB) is designed and fabricated as the daughter card for system integration. The daughter card carries the designed chip is integrated to ARM versatile platform board and the PCB of MRAM as the system integration and application development environment.

Original languageEnglish
Title of host publication17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
Pages67-70
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007 - Taipei, Taiwan
Duration: 3 Dec 20075 Dec 2007

Publication series

NameRecords of the IEEE International Workshop on Memory Technology, Design and Testing
ISSN (Print)1087-4852

Conference

Conference17th IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2007
CountryTaiwan
CityTaipei
Period3/12/075/12/07

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