An all digital spread spectrum clock generator with programmable spread ratio for SoC applications

Duo Sheng*, Ching Che Chung, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this paper, a programmable all-digital spread spectrum clock generator (ADSSCG) suitable for System-On- Chip (SoC) applications with ultra-low-power capability is presented. Based on the timing constraint of system, the programmable ADSSCG can provide the suitable frequency spread ratio to obtain the optimal combination of timing deviation and EMI reduction for system applications. Besides, the proposed ADSSCG employs an ultra-low-power digitally controlled oscillator (DCO) to save overall power consumption to 560μW (@400MHz) and the peak EMI power reduction is large than 25dB. In addition, the proposed ADSSCG can be implemented only with standard cells; as a result, the area can be saved without any passive component, and making it easily portable to different processes and very suitable for SoC applications.

Original languageEnglish
Title of host publicationProceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
Pages850-853
Number of pages4
DOIs
StatePublished - 1 Dec 2008
EventAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao, China
Duration: 30 Nov 20083 Dec 2008

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

ConferenceAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
CountryChina
CityMacao
Period30/11/083/12/08

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