An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

Yi Wei Lin*, Ming Chien Tsai, Hao I. Yang, Geng Cing Lin, Shao Cheng Wang, Ching Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan Chun Lien, Kuen Di Lee, Wei Chiang Shih

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We present an all-digital Read Stability and Write Margin (WM) characterization scheme for CMOS 6T SRAM array. The scheme measures the cell Read Disturb voltage (V read ) and cell Inverter Trip voltage (V trip ) in SRAM cell array environment. Measured voltages are converted to frequency with Voltage Controlled Oscillator (VCO) and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. Resistor based voltage divider with 64 voltage levels and 10mV per step is employed to allow sweeping of BL voltage from 640mV to GND for WM characterization. A 512Kb test macro is implemented in UMC 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations validate the accuracy of V read and V trip measurement scheme, and post-layout simulations show the resolution of the digital read-out scheme is 0.167mV/bit.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
StatePublished - 25 Jul 2012
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 23 Apr 201225 Apr 2012

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan
CityHsinchu
Period23/04/1225/04/12

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