An all-digital phase-locked loop with high-resolution for SoC applications

Duo Sheng*, Ching Che Chung, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

22 Scopus citations

Abstract

In this paper, we propose a very high-resolution all-digital phase-locked loop (ADPLL), which is designed with the cell library and described by Hardware Description Language (HDL). The proposed ADPLL uses a novel digitally controlled oscillator (DCO) to achieve 1.06ps resolution and the proposed DCO can extend the controllable range easily. The dead zone of the proposed phase/frequency detector (PFD) is 5ps. The proposed ADPLL can be easily ported to different process as a soft intellectual property (IP) block, making it very suitable for System-On-Chip (SoC) and system-level applications.

Original languageEnglish
Title of host publication2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages207-210
Number of pages4
DOIs
StatePublished - 1 Oct 2007
Event2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan
Duration: 26 Apr 200728 Apr 2007

Publication series

Name2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
CountryTaiwan
CityHsinchu
Period26/04/0728/04/07

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