An all-digital phase-locked loop with a multi-delay-switching TDC

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a low-power time-to-digital converter (TDC) with multi-delay-switching mechanism for ADPLL application. In order to achieve low power dissipation and low area occupation, a switching mechanism is proposed on TDC design. The proposed ADPLL achieves the frequency range from 150 MHz to 1.45 GHz and 18.4 ps peak-to-peak jitter at 800 MHz. The design has been implemented in 0.18 um CMOS process with an active area of 0.1088 mm2 and the whole system consumes 8.41 mW at 800 MHz.

Original languageEnglish
Title of host publication2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509039692
DOIs
StatePublished - 5 Jun 2017
Event2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 - Hsinchu, Taiwan
Duration: 24 Apr 201727 Apr 2017

Publication series

Name2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017

Conference

Conference2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017
CountryTaiwan
CityHsinchu
Period24/04/1727/04/17

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    Su, C. C., Lin, C-C., & Hung, C-C. (2017). An all-digital phase-locked loop with a multi-delay-switching TDC. In 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 [7939662] (2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2017.7939662