An all-digital phase-locked loop for high-speed clock generation

Ching Che Chung; Chen-Yi Lee

doi:10.1109/JSSC.2002.807398

An all-digital phase-locked loop for high-speed clock generation

Ching Che Chung^*, Chen-Yi Lee

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Conference article

5 Scopus citations

Abstract

An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this paper. The proposed ADPLL architecture can be implemented with standard cells. And the ADPLL implemented in a 0.35μm 1P4M CMOS process can operate from 40MHz to 540MHz. The p-p jitter of the output clock is less than ±170ps, and the rms jitter of the output clock is less than 39ps. A systematic way to design the ADPLL with specified standard cell library is also introduced. The proposed ADPLL can easily be ported to different processes in a short time. Thus it can reduce the design time and design complexity of ADPLL, making it very suitable for System-On-Chip (SoC) applications.

Original language	English
Pages (from-to)	679-682
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
DOIs	https://doi.org/10.1109/JSSC.2002.807398
State	Published - 1 Jan 2002
Event	2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: 26 May 2002 → 29 May 2002

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Chung, C. C., & Lee, C-Y. (2002). An all-digital phase-locked loop for high-speed clock generation. Proceedings - IEEE International Symposium on Circuits and Systems, 3, 679-682. https://doi.org/10.1109/JSSC.2002.807398

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abstract = "An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this paper. The proposed ADPLL architecture can be implemented with standard cells. And the ADPLL implemented in a 0.35μm 1P4M CMOS process can operate from 40MHz to 540MHz. The p-p jitter of the output clock is less than ±170ps, and the rms jitter of the output clock is less than 39ps. A systematic way to design the ADPLL with specified standard cell library is also introduced. The proposed ADPLL can easily be ported to different processes in a short time. Thus it can reduce the design time and design complexity of ADPLL, making it very suitable for System-On-Chip (SoC) applications.",

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N2 - An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this paper. The proposed ADPLL architecture can be implemented with standard cells. And the ADPLL implemented in a 0.35μm 1P4M CMOS process can operate from 40MHz to 540MHz. The p-p jitter of the output clock is less than ±170ps, and the rms jitter of the output clock is less than 39ps. A systematic way to design the ADPLL with specified standard cell library is also introduced. The proposed ADPLL can easily be ported to different processes in a short time. Thus it can reduce the design time and design complexity of ADPLL, making it very suitable for System-On-Chip (SoC) applications.

AB - An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented in this paper. The proposed ADPLL architecture can be implemented with standard cells. And the ADPLL implemented in a 0.35μm 1P4M CMOS process can operate from 40MHz to 540MHz. The p-p jitter of the output clock is less than ±170ps, and the rms jitter of the output clock is less than 39ps. A systematic way to design the ADPLL with specified standard cell library is also introduced. The proposed ADPLL can easily be ported to different processes in a short time. Thus it can reduce the design time and design complexity of ADPLL, making it very suitable for System-On-Chip (SoC) applications.

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