An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems

Jui Yuan Yu*, Juinn Ting Chen, Mei Hui Yang, Ching Che Chung, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

An all-digital clock generator is designed to enable the clock phase and frequency tuning dynamically during the wireless communications system is in operation. This phase-frequency tunable clock generator (PFTCG) provides 8 clock phases for selection and enables the ADC circuits sampling signals with lower frequency and better sampling phase, resulting in lower power consumption. The PFTCG provides the frequency tuning range ±150ppm centered at 5MHz, resulting in high performance due to smaller sampling clock offset. This PFTCG is simulated under the wireless body area network system, and shows a 6.3dB SNR improvement at BER=1e-3, and the hardware is simulated with power 77.56μW in the standard process 90nm CMOS technology.

Original languageEnglish
Title of host publicationProceedings - 20th Anniversary IEEE International SOC Conference
Pages305-308
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan
Duration: 26 Sep 200729 Sep 2007

Publication series

NameProceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference20th Anniversary IEEE International SOC Conference
CountryTaiwan
CityHsinchu
Period26/09/0729/09/07

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  • Cite this

    Yu, J. Y., Chen, J. T., Yang, M. H., Chung, C. C., & Lee, C-Y. (2007). An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems. In Proceedings - 20th Anniversary IEEE International SOC Conference (pp. 305-308). [4545480] (Proceedings - 20th Anniversary IEEE International SOC Conference). https://doi.org/10.1109/SOCC.2007.4545480