An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

Geng Cing Lin*, Shao Cheng Wang, Yi Wei Lin, Ming Chien Tsai, Ching Te Chuang, Shyh-Jye Jou, Nan Chun Lien, Wei Chiang Shih, Kuen Di Lee, Jyun Kai Chu

*Corresponding author for this work

Research output: Contribution to conferencePaper

1 Scopus citations

Abstract

We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (V TH ) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the V TH measurement scheme is about 2-7mV at TT corner across temperature range from 85°C to 45°C, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit. Measured VTH distributions agree well with Monte Carlo simulation results.

Original languageEnglish
Pages2485-2488
Number of pages4
DOIs
StatePublished - 28 Sep 2012
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period20/05/1223/05/12

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    Lin, G. C., Wang, S. C., Lin, Y. W., Tsai, M. C., Chuang, C. T., Jou, S-J., Lien, N. C., Shih, W. C., Lee, K. D., & Chu, J. K. (2012). An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. 2485-2488. Paper presented at 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271804