An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression

Yanghyo Kim; Gyung Su Byun; Adrian Tang; Chewn Pu Jou; Hsieh Hung Hsieh; Glenn Reinman; Jason Cong; Mau-Chung Chang

doi:10.1109/ISSCC.2012.6176874

An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression

Yanghyo Kim^*, Gyung Su Byun, Adrian Tang, Chewn Pu Jou, Hsieh Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Chang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

The demand for higher power efficiency and bandwidth is increasing as mobile devices keep enhancing its graphic computing and media processing capabilities. Current memory interfaces with single-wire signaling operate at 5Gb/s/pin [1] and 6Gb/s/pin [2] with the power efficiency of 17.4pJ/b/pin and 15.8pJ/b/pin, respectively. Mobile DDR memory I/O with differential signaling has better power efficiency of 6.4pJ/b/pin [3], and so does the prior dual-band interconnect (DBI) [4] with the efficiency of 5pJ/b/pin at 4.2Gb/s/pin for simultaneous bidirectional (SBD) mobile memory I/O interface. However, DBI's differential signaling is incompatible with existing standards, and it also occupies large die area for using differential transmission lines and an LC-oscillator for generating RF-carrier. To alleviate these concerns, we propose to use a Single-Transmission-Line DBI (STL-DBI) with the best figure-of-merit (FoM) defined as data rate per pin divided by the I/O-interface die area and power consumption.

Original language	English
Title of host publication	2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
Pages	50-51
Number of pages	2
DOIs	https://doi.org/10.1109/ISSCC.2012.6176874
State	Published - 11 May 2012
Event	59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States Duration: 19 Feb 2012 → 23 Feb 2012

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	55
ISSN (Print)	0193-6530

Conference

Conference	59th International Solid-State Circuits Conference, ISSCC 2012
Country	United States
City	San Francisco, CA
Period	19/02/12 → 23/02/12

Access to Document

10.1109/ISSCC.2012.6176874

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Kim, Y., Byun, G. S., Tang, A., Jou, C. P., Hsieh, H. H., Reinman, G., Cong, J., & Chang, M-C. (2012). An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers (pp. 50-51). [6176874] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55). https://doi.org/10.1109/ISSCC.2012.6176874

Kim, Yanghyo ; Byun, Gyung Su ; Tang, Adrian ; Jou, Chewn Pu ; Hsieh, Hsieh Hung ; Reinman, Glenn ; Cong, Jason ; Chang, Mau-Chung. / An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. pp. 50-51 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{777c57abbee547f3a56f735bff7b46d8,

title = "An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression",

abstract = "The demand for higher power efficiency and bandwidth is increasing as mobile devices keep enhancing its graphic computing and media processing capabilities. Current memory interfaces with single-wire signaling operate at 5Gb/s/pin [1] and 6Gb/s/pin [2] with the power efficiency of 17.4pJ/b/pin and 15.8pJ/b/pin, respectively. Mobile DDR memory I/O with differential signaling has better power efficiency of 6.4pJ/b/pin [3], and so does the prior dual-band interconnect (DBI) [4] with the efficiency of 5pJ/b/pin at 4.2Gb/s/pin for simultaneous bidirectional (SBD) mobile memory I/O interface. However, DBI's differential signaling is incompatible with existing standards, and it also occupies large die area for using differential transmission lines and an LC-oscillator for generating RF-carrier. To alleviate these concerns, we propose to use a Single-Transmission-Line DBI (STL-DBI) with the best figure-of-merit (FoM) defined as data rate per pin divided by the I/O-interface die area and power consumption.",

author = "Yanghyo Kim and Byun, {Gyung Su} and Adrian Tang and Jou, {Chewn Pu} and Hsieh, {Hsieh Hung} and Glenn Reinman and Jason Cong and Mau-Chung Chang",

year = "2012",

month = may,

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doi = "10.1109/ISSCC.2012.6176874",

language = "English",

isbn = "9781467303736",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

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booktitle = "2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers",

note = "null ; Conference date: 19-02-2012 Through 23-02-2012",

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Kim, Y, Byun, GS, Tang, A, Jou, CP, Hsieh, HH, Reinman, G, Cong, J & Chang, M-C 2012, An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. in 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers., 6176874, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 55, pp. 50-51, 59th International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, United States, 19/02/12. https://doi.org/10.1109/ISSCC.2012.6176874

An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. / Kim, Yanghyo; Byun, Gyung Su; Tang, Adrian; Jou, Chewn Pu; Hsieh, Hsieh Hung; Reinman, Glenn; Cong, Jason; Chang, Mau-Chung.

2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. p. 50-51 6176874 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 55).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Kim Y, Byun GS, Tang A, Jou CP, Hsieh HH, Reinman G et al. An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers. 2012. p. 50-51. 6176874. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2012.6176874