An 8.8-GS/s 8b time-interleaved SAR ADC with 50-dB SFDR using complementary dual-loop-assisted buffers in 28nm CMOS

X. Shawn Wang*, Chi Hang Chan, Jieqiong Du, Chien Heng Wong, Yilei Li, Yuan Du, Yen-Cheng Kuan, Boyu Hu, Mau-Chung Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an 8.8 GS/s 16-way time-interleaved asynchronous SAR ADC fabricated in 28-nm CMOS technology. A two-level 2×8 master-slave hierarchical interleaved architecture is employed. A complementary dual-loop-assisted buffer is proposed to achieve both high linearity and bandwidth with low power. This time-interleaved ADC achieves 38.4-dB SNDR and 50-dB SFDR with a Nyquist input at 8.8 GS/s sampling rate and consumes 83.4 mW, resulting in a 140 fJ/conv.-step Walden FOM with buffers.

Original languageEnglish
Title of host publicationProceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018
EditorsSteven Turner, Andre Hanke Hanke
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages88-91
Number of pages4
ISBN (Print)9781538645451
DOIs
StatePublished - 7 Aug 2018
Event2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018 - Philadelphia, United States
Duration: 10 Jun 201812 Jun 2018

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume2018-June
ISSN (Print)1529-2517

Conference

Conference2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018
CountryUnited States
CityPhiladelphia
Period10/06/1812/06/18

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    Wang, X. S., Chan, C. H., Du, J., Wong, C. H., Li, Y., Du, Y., Kuan, Y-C., Hu, B., & Chang, M-C. (2018). An 8.8-GS/s 8b time-interleaved SAR ADC with 50-dB SFDR using complementary dual-loop-assisted buffers in 28nm CMOS. In S. Turner, & A. H. Hanke (Eds.), Proceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018 (pp. 88-91). [8429007] (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIC.2018.8429007