An 865-μW H.264/AVC video decoder for mobile applications

Tsu Ming Liu*, Ting An Lin, Sheng Zen Wang, Wen Ping Lee, Kang Cheng Hou, Jiun Yan Yang, Chen Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

24 Scopus citations

Abstract

A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quarter-common intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865μW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on 4×4 sub-block level pipelining that achieves better buffer allocation and decoding throughput. In addition, several modules are designed with new features to improve overall system throughput (up to 260,000 Macro-Block/sec). The proposed solution integrates 456-k logic gates with 161Kb of embedded SRAM in 0.18-μm single-poly six-metal CMOS process with area of 11.3mm2.

Original languageEnglish
Title of host publication2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005
PublisherIEEE Computer Society
Pages301-304
Number of pages4
ISBN (Print)0780391624, 9780780391628
DOIs
StatePublished - 1 Jan 2005
Event1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005 - Hsinchu, Taiwan
Duration: 1 Nov 20053 Nov 2005

Publication series

Name2005 IEEE Asian Solid-State Circuits Conference, ASSCC 2005

Conference

Conference1st IEEE Asian Solid-State Circuits Conference, ASSCC 2005
CountryTaiwan
CityHsinchu
Period1/11/053/11/05

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