A low power H.264/AVC video decoder LSI for mobile applications is presented. Video decoding of quarter-common intermediate format (QCIF) sequence at 30 frames per second is achieved at 1.2MHz clock frequency and requires about 865μW at 1.8-V supply voltage. Moreover, CIF, SD and HD sequence format are also supported. The decoder architecture is based on 4×4 sub-block level pipelining that achieves better buffer allocation and decoding throughput. In addition, several modules are designed with new features to improve overall system throughput (up to 260,000 Macro-Block/sec). The proposed solution integrates 456-k logic gates with 161Kb of embedded SRAM in 0.18-μm single-poly six-metal CMOS process with area of 11.3mm2.