An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (base+RF) band signaling

Gyung Su Byun*, Yanghyo Kim, Jongsun Kim, Sai Wang Tam, H. H. Hsieh, P. Y. Wu, C. Jou, Jason Cong, Glenn Reinman, Mau-Chung Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

14 Scopus citations

Abstract

Power and bandwidth requirements have become more stringent for DRAMs in recent years. This is largely because mobile devices (such as smart phones) are more intensively relying on the use of graphics. Current DDR memory I/Os operate at 5Gb/s with a power efficiency of 17.4mW/Gb/s (i.e., 17.4pJ/b)[1], and graphic DRAM I/Os operate at 7Gb/s/pin [3] with a power efficiency worse than that of DDR. High-speed serial links [5], with a better power efficiency of ∼1mW/Gb/s, would be favored for mobile memory I/O interface. However, serial links typically require long initialization time (∼1000 clock cycles), and do not meet mobile DRAM I/O requirements for fast switching between active, standby, self-refresh and power-down operation modes [4]. Also, traditional baseband-only (or BB-only) signaling tends to consume power super-linearly [4] for extended bandwidth due to the need of power hungry pre-emphasis, and equalization circuits.

Original languageEnglish
Title of host publication2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
Pages488-489
Number of pages2
DOIs
StatePublished - 12 May 2011
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: 20 Feb 201124 Feb 2011

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
CountryUnited States
CitySan Francisco, CA
Period20/02/1124/02/11

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