An 8 Gbps fast-locked automatic gain control for PAM receiver

Guo Wei Wu*, Wei-Zen Chen, Shih Hao Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0,18 m CMOS technology, the chip size is 0.62 mm × 0.62 mm. The total power dissipation is 84 m W from a 1.8 V supply.

Original languageEnglish
Title of host publicationProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
Pages173-176
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009 - Taipei, Taiwan
Duration: 16 Nov 200918 Nov 2009

Publication series

NameProceedings of Technical Papers - 2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009

Conference

Conference2009 IEEE Asian Solid-State Circuits Conference, A-SSCC 2009
CountryTaiwan
CityTaipei
Period16/11/0918/11/09

Keywords

  • Automatic gain control (AGC)
  • PAM receiver
  • Variable gain amplifier

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