This brief presents a 65-nm CMOS single-channel 8-bit ADC compatible for energy-efficient high-speed compressive sensing (CS) and Nyquist sampling (NS). A self-Timed pipeline two-stage SAR-binary-search architecture is proposed and integrated with a 4-GHz random-matrix clock generator, enabling a physical sampling speed up to 500 MS/s with 40.2-dB SNDR in NS-mode and an equivalent speed up to 4 GS/s with 36.2-dB SNDR in CS-mode, leading to FOMs of 239 fJ/conversion-step and 71 fJ/conversion-step, respectively. A passive-charge-sharing with open-loop residue-Amplifier technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to predistort interstage errors.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - 1 Oct 2016|
- compressive sensing (CS)
- SAR-binary-search (BS)
- self-Timed pipeline