An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen Cheng Kuan, Yong Qu, Mau Chung Frank Chang, Jieh-Tsorng Wu, Shiuh Hua Wood Chiang

Research output: Contribution to journalArticlepeer-review

Abstract

An 8-bit 10-GHz 8x time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) with grouped capacitors in a symmetrical structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A detailed study rigorously analyzes the effect of gradient on the proposed DAC layout. The DAC additionally implements quantized sub-radix-2 scaling with redistributed redundancy. A high-speed dual-path bootstrapped switch decouples the critical signal from the nonlinear parasitic capacitance to boost the sampling spurious-free dynamic range by more than 5 dB. Fabricated in a 28-nm CMOS process, the ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding a figure-of-merit of 37 fJ/conv.-step, the best among state-of-the-arts.

Original languageEnglish
JournalIEEE Journal of Solid-State Circuits
DOIs
StateAccepted/In press - 2021

Keywords

  • Analog-to-digital converter (ADC)
  • bootstrapped switch
  • Capacitors
  • Delays
  • digital-to-analog converter (DAC)
  • gradient
  • high-speed ADC
  • Layout
  • matching
  • Metals
  • Parasitic capacitance
  • parasitic capacitance
  • Power demand
  • successive-approximation register (SAR) ADC
  • Switches
  • time-interleaved ADC.

Fingerprint Dive into the research topics of 'An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch'. Together they form a unique fingerprint.

Cite this