An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC with Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen Cheng Kuan, Mau Chung Frank Chang, Jieh Tsorng Wu*, Shiuh Hua Wood Chiang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW,yielding an FoM of 37 fJ/conv.-step,the lowest among the reported ADCs with similar speeds and resolutions and more than 2× improvement from the state-of-the-art.

Original languageEnglish
Title of host publicationESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages83-86
Number of pages4
ISBN (Electronic)9781728115504
DOIs
StatePublished - Sep 2019
Event45th IEEE European Solid State Circuits Conference, ESSCIRC 2019 - Cracow, Poland
Duration: 23 Sep 201926 Sep 2019

Publication series

NameESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference

Conference

Conference45th IEEE European Solid State Circuits Conference, ESSCIRC 2019
CountryPoland
CityCracow
Period23/09/1926/09/19

Keywords

  • Bootstrapped switch
  • DAC
  • SAR ADC
  • time interleaved

Fingerprint Dive into the research topics of 'An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC with Grouped DAC Capacitors and Dual-Path Bootstrapped Switch'. Together they form a unique fingerprint.

Cite this