TY - JOUR

T1 - An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC with Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC

AU - Kuo, Hsuan Lun

AU - Lu, Chih Wen

AU - Chen, Poki

N1 - Publisher Copyright:
© 2013 IEEE.

PY - 2021

Y1 - 2021

N2 - A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise and incomplete digital-to-analog converter (DAC) switching settling. To reduce the total capacitance, all capacitor values of the 12-bit DAC were divided by 16, and a parallel-series capacitor scheme was used to implement these noninteger capacitors. The 12-bit SAR ADC prototype was fabricated using 0.18- mu text{m} 1P6M complementary metal oxide semiconductor technology. The maximal differential nonlinearity and integral nonlinearity were measured as -0.4/0.54 and -0.81/0.89 LSB, respectively, where 1,,text {LSB} = 0.488 mV. The signal-to-noise-and-distortion ratio and effective number of bits were 69.51 dB and 11.25 bits, respectively, for the input frequency of 500 kHz and sampling rate of 1 MS/s. The proposed SAR ADC features an 18.39-fJ/conversion-step Figure-of-Merit (FoM) at the sampling rate of 1 MS/s.

AB - A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise and incomplete digital-to-analog converter (DAC) switching settling. To reduce the total capacitance, all capacitor values of the 12-bit DAC were divided by 16, and a parallel-series capacitor scheme was used to implement these noninteger capacitors. The 12-bit SAR ADC prototype was fabricated using 0.18- mu text{m} 1P6M complementary metal oxide semiconductor technology. The maximal differential nonlinearity and integral nonlinearity were measured as -0.4/0.54 and -0.81/0.89 LSB, respectively, where 1,,text {LSB} = 0.488 mV. The signal-to-noise-and-distortion ratio and effective number of bits were 69.51 dB and 11.25 bits, respectively, for the input frequency of 500 kHz and sampling rate of 1 MS/s. The proposed SAR ADC features an 18.39-fJ/conversion-step Figure-of-Merit (FoM) at the sampling rate of 1 MS/s.

KW - multiple-LSB redundant CDAC

KW - non-binary-weighted CDAC

KW - SAR ADC

UR - http://www.scopus.com/inward/record.url?scp=85099233916&partnerID=8YFLogxK

U2 - 10.1109/ACCESS.2020.3048979

DO - 10.1109/ACCESS.2020.3048979

M3 - Article

AN - SCOPUS:85099233916

VL - 9

SP - 5651

EP - 5669

JO - IEEE Access

JF - IEEE Access

SN - 2169-3536

M1 - 9312602

ER -