An 11-bit two-stage hybrid-DAC for TFT LCD column drivers

Ping Yeh Yin, Chih Wen Lu, Chih Yu Hsu, Yo Sheng Lin

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper proposes an 11-bit two-stage hybrid-DAC for high-color-depth LCD column drivers. To save the die area, the proposed DAC is composed of a 7-bit RDAC and a 4-bit cyclic-DAC to render an 11-bit resolution. The worst DNL/INL from post-layout simulation is 0.28/0.34 LSB with 1 LSB = 2.2 mV. A three-stage class-B operational amplifier is connected as a unity-gain buffer to drive highly capacitive column lines of LCD panel. The buffer's settling time to settle within 0.2% of the final voltage is less than 4 us. This hybrid-DAC prototype is implemented using 0.35-um CMOS technology with a chip size of 1.36 mm2.

Original languageEnglish
Title of host publicationProceedings - 4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013
Pages631-635
Number of pages5
DOIs
StatePublished - 2013
Event4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013 - Bangkok, Thailand
Duration: 29 Jan 201331 Jan 2013

Publication series

NameProceedings - International Conference on Intelligent Systems, Modelling and Simulation, ISMS
ISSN (Print)2166-0662
ISSN (Electronic)2166-0670

Conference

Conference4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013
CountryThailand
CityBangkok
Period29/01/1331/01/13

Keywords

  • column driver
  • cyclic-DAC
  • DAC
  • LCD
  • operatioal amplifier

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