Alternate hammering test for application-specific DRAMs and an industrial case study

Rei Fu Huang*, Hao Yu Yang, Chia-Tso Chao, Shih Chin Lin

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

11 Scopus citations

Abstract

This paper presents a novel memory test algorithm, named alternate hammering test, to detect the pairwise word-line hammering faults for application-specific DRAMs. Unlike previous hammering tests, which require excessively long test time, the alternate hammering test is designed scalable to industrial DRAM arrays by considering the array layout for potential fault sites and the highest DRAM-access frequency in real system applications. The effectiveness and efficiency of the proposed alternate hammering test are validated through the test application to an eDRAM macro embedded in a storage-application SoC.

Original languageEnglish
Title of host publicationProceedings of the 49th Annual Design Automation Conference, DAC '12
Pages1012-1017
Number of pages6
DOIs
StatePublished - 11 Jul 2012
Event49th Annual Design Automation Conference, DAC '12 - San Francisco, CA, United States
Duration: 3 Jun 20127 Jun 2012

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X

Conference

Conference49th Annual Design Automation Conference, DAC '12
CountryUnited States
CitySan Francisco, CA
Period3/06/127/06/12

Keywords

  • embedded-DRAM
  • hammering test

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