All digital phase-locked loop with modified binary search of frequency acquisition

Shyh-Jye Jou*, Ya Lan Tsao, I. Ying Yang

*Corresponding author for this work

Research output: Contribution to conferencePaper

3 Scopus citations

Abstract

In this paper, the design of an all digital phase-locked loop is proposed. The phase-lock process is separated into frequency acquisition and phase acquisition that significantly reduces the phase-lock time. By using a modified binary search algorithm, it can accomplish phase lock process within 43 input clock cycles. To generate a high frequency digital clock, a digitally controlled oscillator with 14-bits is used. The DCO frequency range is from 250 MHz to over 500 MHz. The whole chip contains about 5000 transistors and the core chip size is 1.2*1.2 mm2.

Original languageEnglish
Pages195-198
Number of pages4
DOIs
StatePublished - 1 Dec 1998
EventProceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology - Lisboa, Portugal
Duration: 7 Sep 199810 Sep 1998

Conference

ConferenceProceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology
CityLisboa, Portugal
Period7/09/9810/09/98

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  • Cite this

    Jou, S-J., Tsao, Y. L., & Yang, I. Y. (1998). All digital phase-locked loop with modified binary search of frequency acquisition. 195-198. Paper presented at Proceedings of the 1998 5th IEEE International Conference on Electronics, Circuits and Systems (ICECS'98) - Surfing the Waves of Science and Technology, Lisboa, Portugal, . https://doi.org/10.1109/ICECS.1998.814861