All-digital phase-locked loop (ADPLL)-based clock recovery circuit

Terng-Yin Hsu, Bai Jue Shieh, Chen-Yi Lee

Research output: Contribution to journalArticlepeer-review

43 Scopus citations


A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6-μm CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clock generator can generate any target clock rate fclock; and 3) the function of nonreturn-to-zero clock recovery has a maximum fclock/4 recovering capability with a locking range of (τinput ± τinput/2), where τinput is the input period.

Original languageEnglish
Pages (from-to)1063-1073
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Issue number8
StatePublished - 1 Aug 1999

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