In this paper, an all digital push-pull linear voltage regulator is proposed that consists of a digital error detector, a voltage divider, a mode indicator, a pull device, and grouped push devices. The digital regulator is suitable for super-to near-threshold region operation by providing a variable output voltage that ranges from 0.5 to 1 V in steps of 0.1 V. The maximum load current is 100 mA for every output level. The current efficiency is 99.8% with only 164.5 μ A quiescent current on UMC 65-nm standard CMOS technology. A response time constraint is developed to provide a design guideline for (all) the digital control system. It describes the correlation between required speed of the digital control system, the output performance and the size of the decoupling capacitor. A time interleaving control technique is then proposed to have a tradeoff between output performance, quiescent current, and the size of decoupling capacitor.
|Number of pages||13|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - 1 Jan 2012|
- Current efficiency
- Linear regulator
- Response time constraint
- Time interleaving