Algorithmic analog-to-digital converter with low ratio- and gain-sensitivities and 4N-clock conversion cycle

Shu Yuan Chin*, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

Abstract

This paper describes a new SC method to reduce the capacitor mismatching error and finite-gain error in an ADC. Through the use of switched-capacitor techniques, the proposed new ADC is insensitive to the capacitor-ratio accuracy as well as the finite gain and the offset voltage of the operational amplifiers. The switching error becomes the only major error source. Moreover, the cycle time for n-bit conversion is reduced to 4n-clock time. Both SWITCAP and Hspice simulations have been performed to verify the performance of the new ADC. It is shown that a 15-bit resolution at the sampling frequency of 20 KHz can be achieved when the capacitor ratios have a variation of 1% and the finite gain of the op amps is only 66 dB.

Original languageEnglish
Pages (from-to)325-328
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
DOIs
StatePublished - 1 Dec 1994
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: 30 May 19942 Jun 1994

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