Air spacer MOSFET technology for 20nm node and beyond

Jemin Park; Chen-Ming Hu

doi:10.1109/ICSICT.2008.4734461

Air spacer MOSFET technology for 20nm node and beyond

Jemin Park^*, Chen-Ming Hu

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Scopus citations

Abstract

Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20nm-gate transistor. One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies. With 10nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer and oxide-spacer technologies respectively. Furthermore, the switching energy (power consumption) is reduced by 46% and 33% respectively. The other is SAC process with air spacer. 3D mixed mode simulation shows that the 35% area benefit can be retained while improving the speed and switching energy by 75% to be 10% better than a non-SAC device.

Original language	English
Title of host publication	ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings
Pages	53-56
Number of pages	4
DOIs	https://doi.org/10.1109/ICSICT.2008.4734461
State	Published - 1 Dec 2008
Event	2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 - Beijing, China Duration: 20 Oct 2008 → 23 Oct 2008

Publication series

Name	International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Conference

Conference	2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008
Country	China
City	Beijing
Period	20/10/08 → 23/10/08

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title = "Air spacer MOSFET technology for 20nm node and beyond",

abstract = "Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20nm-gate transistor. One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies. With 10nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer and oxide-spacer technologies respectively. Furthermore, the switching energy (power consumption) is reduced by 46% and 33% respectively. The other is SAC process with air spacer. 3D mixed mode simulation shows that the 35% area benefit can be retained while improving the speed and switching energy by 75% to be 10% better than a non-SAC device.",

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Park, J & Hu, C-M 2008, Air spacer MOSFET technology for 20nm node and beyond. in ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings., 4734461, International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT, pp. 53-56, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008, Beijing, China, 20/10/08. https://doi.org/10.1109/ICSICT.2008.4734461

Air spacer MOSFET technology for 20nm node and beyond. / Park, Jemin; Hu, Chen-Ming.

ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings. 2008. p. 53-56 4734461 (International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Air spacer MOSFET technology for 20nm node and beyond

AU - Park, Jemin

AU - Hu, Chen-Ming

PY - 2008/12/1

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N2 - Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20nm-gate transistor. One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies. With 10nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer and oxide-spacer technologies respectively. Furthermore, the switching energy (power consumption) is reduced by 46% and 33% respectively. The other is SAC process with air spacer. 3D mixed mode simulation shows that the 35% area benefit can be retained while improving the speed and switching energy by 75% to be 10% better than a non-SAC device.

AB - Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20nm-gate transistor. One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies. With 10nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer and oxide-spacer technologies respectively. Furthermore, the switching energy (power consumption) is reduced by 46% and 33% respectively. The other is SAC process with air spacer. 3D mixed mode simulation shows that the 35% area benefit can be retained while improving the speed and switching energy by 75% to be 10% better than a non-SAC device.

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T3 - International Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

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BT - ICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings

Y2 - 20 October 2008 through 23 October 2008

ER -

Air spacer MOSFET technology for 20nm node and beyond

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