Air spacer MOSFET technology for 20nm node and beyond

Jemin Park*, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

17 Scopus citations

Abstract

Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20nm-gate transistor. One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies. With 10nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer and oxide-spacer technologies respectively. Furthermore, the switching energy (power consumption) is reduced by 46% and 33% respectively. The other is SAC process with air spacer. 3D mixed mode simulation shows that the 35% area benefit can be retained while improving the speed and switching energy by 75% to be 10% better than a non-SAC device.

Original languageEnglish
Title of host publicationICSICT 2008 - 2008 9th International Conference on Solid-State and Integrated-Circuit Technology Proceedings
Pages53-56
Number of pages4
DOIs
StatePublished - 1 Dec 2008
Event2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008 - Beijing, China
Duration: 20 Oct 200823 Oct 2008

Publication series

NameInternational Conference on Solid-State and Integrated Circuits Technology Proceedings, ICSICT

Conference

Conference2008 9th International Conference on Solid-State and Integrated-Circuit Technology, ICSICT 2008
CountryChina
CityBeijing
Period20/10/0823/10/08

Fingerprint Dive into the research topics of 'Air spacer MOSFET technology for 20nm node and beyond'. Together they form a unique fingerprint.

Cite this