AES-based security coprocessor IC in 0.18-μm CMOS with resistance to differential power analysis side-channel attacks

David D. Hwang*, Kris Tiri, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede

*Corresponding author for this work

Research output: Contribution to journalArticle

102 Scopus citations

Abstract

Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DFA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1500 000 encryptions.

Original languageEnglish
Pages (from-to)781-790
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number4
DOIs
StatePublished - 1 Apr 2006

Keywords

  • Advanced Encryption Standard (AES)
  • Biometrics
  • Cryptography
  • Differential power analysis
  • Security
  • Side-channel attacks

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