Advanced layout design for deep-submicron CMOS output buffer with higher driving capability and better ESD reliability

Ming-Dou Ker*, Chung-Yu Wu, Tung Yang Chen

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.

Original languageEnglish
Pages45-49
Number of pages5
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
Duration: 3 Jun 19975 Jun 1997

Conference

ConferenceProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
CityTaipei, China
Period3/06/975/06/97

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