Add to Marked List 1 of 1 Optimal Common-Centroid-Based Unit Capacitor Placements for Yield Enhancement of Switched-Capacitor Circuits

Chien-Chihh Huang, Chin-Long Wey, Jwu E. Chen, Pei-Wen Luo

Research output: Contribution to journalArticle

5 Scopus citations

Abstract

Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion that quickly determines if the placement is optimal. The optimization criterion leads to the development of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal/near-optimal placements on a sufficiently large array size.
Original languageEnglish
Article number17
JournalACM Transactions on Design Automation of Electronic Systems
Volume19
Issue number1
DOIs
StatePublished - Dec 2013

Keywords

  • Design; Algorithms; Performance; Mismatch; common centroid; spatial correlation; process variation; variance of ratio; placement optimization; yield enhancement

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