The jitter of the sampling clock of an analog-to-digital converter (ADC) is measured by a stochastic time-to-digital converter (TDC). The measured jitter data are used to correct the ADC sampling error and improve its signal-to-noise ratio (SNR). The same ADC is used to calibrate the TDC in the background. Both the TDC and the ADC operate at a sampling rate of 80 MS/s. Fabricated in a 65 nm CMOS technology, the TDC consists of 127 timing comparators. The proposed jitter correction technique achieves an equivalent sampling jitter root-mean-squared value (rms) of 4 ps when the jitter rms of the original sampling clock is 8.2 ps.