Adaptive pipeline voltage scaling in high performance microprocessor

Chang Ching Yeh*, Kuei Chung Chang, Tien-Fu Chen, Chingwei Yeh

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

Deep pipeline has traditionally been widely used in high performance microprocessor. To allow continuous program execution, branch prediction provides a necessary method of speculatively executing instructions without compromising performance. However, branch misprediction penalty significantly impacts the performance of the deep pipeline processor. This study presents a new Adaptive Pipeline Voltage Scaling (APVS) technique to reduce branch misprediction penalty. For a likely mispredicted branch entering the processor, APVS begins increasing voltage and merging deep pipeline whereby shorter pipeline length permits less branch misprediction penalty. Once the branch is resolved, the merged stages are split and the supply voltage is reduced again. With dedicated shorter pipeline length within each branch misprediction, APVS achieves great performance improvement. The evaluation of APVS in a 13-stage superscalar processor with benchmarks from SPEC2000 applications shows a performance improvement (between 3-12%, average 8%) over baseline processor that does not exploit APVS.

Original languageEnglish
Pages (from-to)1817-1834
Number of pages18
JournalJournal of Circuits, Systems and Computers
Volume19
Issue number8
DOIs
StatePublished - 1 Dec 2010

Keywords

  • Adaptive pipeline depth control
  • branch misprediction penalty
  • dynamic pipeline scaling

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