Active device under bond pad to save I/O layout for high-pin-count SOC

Ming-Dou Ker, Jeng Jie Peng, Hsin Chin Jiang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35 μm one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices under the pads. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads have been measured. After assembled in wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count system-on-a-chip (SOC).

Original languageEnglish
Title of host publicationProceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003
PublisherIEEE Computer Society
Pages241-246
Number of pages6
ISBN (Electronic)0769518818
DOIs
StatePublished - 1 Jan 2003
Event2003 4th International Symposium on Quality Electronic Design, ISQED 2003 - San Jose, United States
Duration: 24 Mar 200326 Mar 2003

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2003-January
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference2003 4th International Symposium on Quality Electronic Design, ISQED 2003
CountryUnited States
CitySan Jose
Period24/03/0326/03/03

Keywords

  • Bonding
  • CMOS process
  • Electrostatic discharge
  • Leakage current
  • MOS devices
  • Protection
  • Stress
  • System-on-a-chip
  • Testing
  • Threshold voltage

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