Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack

C. H. Cheng*, K. I. Chou, Albert Chin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (Vt) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO 2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.

Original languageEnglish
Pages (from-to)111-114
Number of pages4
JournalSolid-State Electronics
Volume82
DOIs
StatePublished - 25 Mar 2013

Keywords

  • CeO
  • Gate first
  • Small EOT
  • TiLaO

Fingerprint Dive into the research topics of 'Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO <sub>2</sub> gate stack'. Together they form a unique fingerprint.

Cite this