Accurate MOS device hot carrier models for VLSI reliability simulation

Steve S. Chung*, J. J. Yang, J. S. Su

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

3 Scopus citations


This paper describes a Spice-compatible circuit reliability simulation model of submicron LDD MOS devices. It incorporates an accurate hot carrier model of the degraded MOSFET characteristics under long term operations, which includes a drain current model and a substrate current model. The drain current reduction is modeled as mobility degradation due to interface states enhanced scattering. The substrate current model is developed based on a new effective electric field concept which shows a significant improvement to the conventional local field model. By characterizing the time-dependent of the device parameters, hot carrier I-V model can be obtained. Comparison of the modeled results with those of experimental shows excellent match for a wide range of device channel length, bias conditions and stress time. Moreover, the reliability simulator that we developed allows prediction of lifetime or aging of a device or circuit in VLSI design.

Original languageEnglish
Pages (from-to)233-236
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - 1 Jan 1995
EventProceedings of the 1995 17th Annual Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 1 May 19954 May 1995

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