Accurate models for CMOS scaling and gate delay in deep sub-micron regime

Kai Chen; Chen-Ming Hu; Peng Fang; Ashawant Gupta; Ming Ren Lin; Donald L. Wollesen

doi:10.1109/SISPAD.1997.621387

Accurate models for CMOS scaling and gate delay in deep sub-micron regime

Kai Chen^*, Chen-Ming Hu, Peng Fang, Ashawant Gupta, Ming Ren Lin, Donald L. Wollesen

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Contribution to conference › Paper

Abstract

Accurate models for drain saturation current including velocity saturation, finite thickness of inversion layer due to quantization effect, mobility degradation due to vertical electrical field in the channel, and parasitic S/D series resistance, and their experimental confirmation with measurement data are presented. Furthermore, models for load capacitance and CMOS propagation delay are proposed and experimentally confirmed.

Original language	English
Pages	261-264
Number of pages	4
DOIs	https://doi.org/10.1109/SISPAD.1997.621387
State	Published - 1 Jan 1997
Event	Proceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD'97 - Cambridge, MA, USA Duration: 8 Sep 1997 → 10 Sep 1997

Conference

Conference	Proceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD'97
City	Cambridge, MA, USA
Period	8/09/97 → 10/09/97

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10.1109/SISPAD.1997.621387

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Chen, K., Hu, C-M., Fang, P., Gupta, A., Lin, M. R., & Wollesen, D. L. (1997). Accurate models for CMOS scaling and gate delay in deep sub-micron regime. 261-264. Paper presented at Proceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD'97, Cambridge, MA, USA, . https://doi.org/10.1109/SISPAD.1997.621387

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abstract = "Accurate models for drain saturation current including velocity saturation, finite thickness of inversion layer due to quantization effect, mobility degradation due to vertical electrical field in the channel, and parasitic S/D series resistance, and their experimental confirmation with measurement data are presented. Furthermore, models for load capacitance and CMOS propagation delay are proposed and experimentally confirmed.",

author = "Kai Chen and Chen-Ming Hu and Peng Fang and Ashawant Gupta and Lin, {Ming Ren} and Wollesen, {Donald L.}",

year = "1997",

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doi = "10.1109/SISPAD.1997.621387",

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Chen, K, Hu, C-M, Fang, P, Gupta, A, Lin, MR & Wollesen, DL 1997, 'Accurate models for CMOS scaling and gate delay in deep sub-micron regime', Paper presented at Proceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD'97, Cambridge, MA, USA, 8/09/97 - 10/09/97 pp. 261-264. https://doi.org/10.1109/SISPAD.1997.621387

Accurate models for CMOS scaling and gate delay in deep sub-micron regime. / Chen, Kai; Hu, Chen-Ming; Fang, Peng; Gupta, Ashawant; Lin, Ming Ren; Wollesen, Donald L.

1997. 261-264 Paper presented at Proceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD'97, Cambridge, MA, USA, .

Research output: Contribution to conference › Paper

TY - CONF

T1 - Accurate models for CMOS scaling and gate delay in deep sub-micron regime

AU - Chen, Kai

AU - Hu, Chen-Ming

AU - Fang, Peng

AU - Gupta, Ashawant

AU - Lin, Ming Ren

AU - Wollesen, Donald L.

PY - 1997/1/1

Y1 - 1997/1/1

N2 - Accurate models for drain saturation current including velocity saturation, finite thickness of inversion layer due to quantization effect, mobility degradation due to vertical electrical field in the channel, and parasitic S/D series resistance, and their experimental confirmation with measurement data are presented. Furthermore, models for load capacitance and CMOS propagation delay are proposed and experimentally confirmed.

AB - Accurate models for drain saturation current including velocity saturation, finite thickness of inversion layer due to quantization effect, mobility degradation due to vertical electrical field in the channel, and parasitic S/D series resistance, and their experimental confirmation with measurement data are presented. Furthermore, models for load capacitance and CMOS propagation delay are proposed and experimentally confirmed.

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DO - 10.1109/SISPAD.1997.621387

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EP - 264

Y2 - 8 September 1997 through 10 September 1997

ER -