Abstract
Accurate models for drain saturation current including velocity saturation, finite thickness of inversion layer due to quantization effect, mobility degradation due to vertical electrical field in the channel, and parasitic S/D series resistance, and their experimental confirmation with measurement data are presented. Furthermore, models for load capacitance and CMOS propagation delay are proposed and experimentally confirmed.
Original language | English |
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Pages | 261-264 |
Number of pages | 4 |
DOIs | |
State | Published - 1 Jan 1997 |
Event | Proceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD'97 - Cambridge, MA, USA Duration: 8 Sep 1997 → 10 Sep 1997 |
Conference
Conference | Proceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD'97 |
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City | Cambridge, MA, USA |
Period | 8/09/97 → 10/09/97 |