Accurate models for CMOS scaling and gate delay in deep sub-micron regime

Kai Chen*, Chen-Ming Hu, Peng Fang, Ashawant Gupta, Ming Ren Lin, Donald L. Wollesen

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

Accurate models for drain saturation current including velocity saturation, finite thickness of inversion layer due to quantization effect, mobility degradation due to vertical electrical field in the channel, and parasitic S/D series resistance, and their experimental confirmation with measurement data are presented. Furthermore, models for load capacitance and CMOS propagation delay are proposed and experimentally confirmed.

Original languageEnglish
Pages261-264
Number of pages4
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD'97 - Cambridge, MA, USA
Duration: 8 Sep 199710 Sep 1997

Conference

ConferenceProceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD'97
CityCambridge, MA, USA
Period8/09/9710/09/97

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    Chen, K., Hu, C-M., Fang, P., Gupta, A., Lin, M. R., & Wollesen, D. L. (1997). Accurate models for CMOS scaling and gate delay in deep sub-micron regime. 261-264. Paper presented at Proceedings of the 1997 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD'97, Cambridge, MA, USA, . https://doi.org/10.1109/SISPAD.1997.621387