Accelerating manycore simulation by efficient NoC interconnection partition on FPGA simulation platform

Wei Chun Ku*, Tien-Fu Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Manycore architecture is the trend of system design. However, manycore simulators face the important issue than general multicore simulators is simulation speed. Several studies provide a FPGA simulation methodology to solve it, but they almost do it by providing a new internal design of core. And some of them don't care the correctness without interconnection simulation. This paper provides a PVCT module and NIP methodology to solve these two issues. According to our experiment, we could provide a 91.4 MIPS simulation performance averagely with Splash2 benchmark by three physical cores. The number of three is decided by capability of Xilinx XC2V8000 FPGA chip.

Original languageEnglish
Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages316-319
Number of pages4
DOIs
StatePublished - 28 Jun 2011
Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
Duration: 25 Apr 201128 Apr 2011

Publication series

NameProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
CountryTaiwan
CityHsinchu
Period25/04/1128/04/11

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    Ku, W. C., & Chen, T-F. (2011). Accelerating manycore simulation by efficient NoC interconnection partition on FPGA simulation platform. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 (pp. 316-319). [5783638] (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011). https://doi.org/10.1109/VDAT.2011.5783638