A wide-range burst mode clock and data recovery circuit

Wei-Zen Chen; Chin Yuan Wei; Jen Wen Chen

doi:10.1109/ASSCC.2006.357936

A wide-range burst mode clock and data recovery circuit

Wei-Zen Chen^*, Chin Yuan Wei, Jen Wen Chen

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 ^-10.

Original language	English
Pages	403-406
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357936
State	Published - 1 Dec 2006
Event	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 13 Nov 2006 → 15 Nov 2006

Conference

Conference	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
Country	China
City	Hangzhou
Period	13/11/06 → 15/11/06

Access to Document

10.1109/ASSCC.2006.357936

Link to publication in Scopus

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title = "A wide-range burst mode clock and data recovery circuit",

abstract = "This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 -10.",

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N2 - This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 -10.

AB - This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 -10.

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