Abstract
This paper describes the design of a 0.625-3.125 Gbps, burst mode clock and data recovery circuit in a 0.18 μm CMOS process. A novel bang-bang PD incorporating binary-search phase acquisition and dynamic loop filter is proposed to achieve rapid phase locking. The measured locking time is less than 1 ns (@ 3.125 Gbps). Integrating with a limiting amplifier and a 1 to 4 demultiplexer on a single chip, the total power dissipation is 78 mW. The input sensitivity of the burst mode receiver is about 30 mV for BER less than 10 -10.
Original language | English |
---|---|
Pages | 403-406 |
Number of pages | 4 |
DOIs | |
State | Published - 1 Dec 2006 |
Event | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 13 Nov 2006 → 15 Nov 2006 |
Conference
Conference | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 |
---|---|
Country | China |
City | Hangzhou |
Period | 13/11/06 → 15/11/06 |