TY - JOUR
T1 - A wide load range and high efficiency switched-capacitor DC-DC converter with pseudo-clock controlled load-dependent frequency
AU - Chen, Wei Chung
AU - Ming, Da Long
AU - Su, Yi Ping
AU - Lee, Yu Huei
AU - Chen, Ke-Horng
PY - 2014/1/1
Y1 - 2014/1/1
N2 - A high efficiency 3.3 V-to-1 V switched-capacitor (SC) step-down DC-DC converter with load-dependent frequency control (LFC) and deep-green mode (DGM) operation is proposed for system-on-a-chip (SoC) application. According to output loading current, the LFC technique can immediately and dynamically adjust the switching frequency through the use of pseudo-clock generator (PCG) and lead-lag detector (LLD) circuit to obtain high power conversion efficiency and small output voltage ripple over a wide loading current range. Therefore, adequate loading current supplying function and output voltage regulation can be guaranteed. Moreover, the DGM operation, similar to pulse skipping mode, can mask the switching clock to reduce power loss at ultra-light loads for further improving power efficiency. The test chip fabricated in 55 nm CMOS process demonstrates that the proposed fast transient converter can deliver wide load range from 10 mA to 250 mA with two small flying capacitors (CF, CF2 =0.1 μ F) and one output capacitor C OUT =1 μ F). The peak conversion efficiency is 89% compared to the ideal value of 91% (3* Vrm OUT V IN). In other words, the peak normalized efficiency is equal to 98%. The overall normalized efficiency is always kept higher than 90% while the output voltage ripple is guaranteed smaller than 30 mV.
AB - A high efficiency 3.3 V-to-1 V switched-capacitor (SC) step-down DC-DC converter with load-dependent frequency control (LFC) and deep-green mode (DGM) operation is proposed for system-on-a-chip (SoC) application. According to output loading current, the LFC technique can immediately and dynamically adjust the switching frequency through the use of pseudo-clock generator (PCG) and lead-lag detector (LLD) circuit to obtain high power conversion efficiency and small output voltage ripple over a wide loading current range. Therefore, adequate loading current supplying function and output voltage regulation can be guaranteed. Moreover, the DGM operation, similar to pulse skipping mode, can mask the switching clock to reduce power loss at ultra-light loads for further improving power efficiency. The test chip fabricated in 55 nm CMOS process demonstrates that the proposed fast transient converter can deliver wide load range from 10 mA to 250 mA with two small flying capacitors (CF, CF2 =0.1 μ F) and one output capacitor C OUT =1 μ F). The peak conversion efficiency is 89% compared to the ideal value of 91% (3* Vrm OUT V IN). In other words, the peak normalized efficiency is equal to 98%. The overall normalized efficiency is always kept higher than 90% while the output voltage ripple is guaranteed smaller than 30 mV.
KW - Deep-green mode (DGM)
KW - Lead-lag detector (LLD)
KW - Load-dependent frequency control (LFC)
KW - Pseudo-clock generator (PCG)
KW - Switched-capacitor (SC)
KW - System-on-a-chip (SoC)
UR - http://www.scopus.com/inward/record.url?scp=84895930864&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2013.2284182
DO - 10.1109/TCSI.2013.2284182
M3 - Article
AN - SCOPUS:84895930864
VL - 61
SP - 911
EP - 921
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 3
M1 - 6648695
ER -