A well-structured modified booth multiplier design

Li Rong Wang*, Shyh-Jye Jou, Chung Len Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

This paper proposes a well-structured modified Booth encoding (MBE) multiplier architecture. The design adopts an improved Booth encoder and selector to achieve an extra-row-removal and a hybrid spare-tree approach to design two's complementation circuit to both reduce the area and improve the speed. Experimental results on a 32 bit multiplier show that it obtains area and power savings of 15.8% and 11.7% respectively over the classical design and of 7.5% and 5.5% respectively over the design of the best performance reported so far.

Original languageEnglish
Title of host publication2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages85-88
Number of pages4
DOIs
StatePublished - 5 Sep 2008
Event2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan
Duration: 23 Apr 200825 Apr 2008

Publication series

Name2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
CountryTaiwan
CityHsinchu
Period23/04/0825/04/08

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  • Cite this

    Wang, L. R., Jou, S-J., & Lee, C. L. (2008). A well-structured modified booth multiplier design. In 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT (pp. 85-88). [4542418] (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT). https://doi.org/10.1109/VDAT.2008.4542418